Infineon Tri core Architecutre

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Architectural Registers

The TriCore architectural registers consist of 32 General-Purpose Registers (GPRs), two 32-bit registers with program status information (PCXI and PSW), and a Program Counter (PC).

Four GPRs have special functions: 
  • D15 is used as an implicit data register
  • A10 is the stack pointer (SP)
  • A11 is the return address register 
  • A15 is the implicit base address register 
PCXI, PSW, and PC are Core Special Function Registers (CSFRs). The PCXI and PSW registers contain status flags, previous execution and protection information.

Memory model:


The TriCore architecture can access up to 4 Gbytes of unified program and I/O (Input/ Output) memory. The address width is 32-bits. The address space is divided into 16 regions or segments (0 through 15). Each segment is 256-Mbytes. The upper four bits of an address select the specific segment. The first 16-Kbytes of each segment can be accessed using either absolute addressing or absolute bit addressing with the bit set and bit clear instructions.































Source:

https://www.infineon.com/dgdl/TC1_3_ArchOverview_1.pdf?fileId=db3a304312bae05f0112be86204c0111


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