chayyakk's

Architectural Registers The TriCore architectural registers consist of 32 General-Purpose Registers (GPRs), two 32-bit registers with program status information (PCXI and PSW), and a Program Counter (PC). Four GPRs have special functions:  D15 is used as an implicit data register A10 is the stack pointer (SP) A11 is the return address register  A15 is the implicit base address register  PCXI, PSW, and PC are Core Special Function Registers (CSFRs). The PCXI and PSW registers contain status flags, previous execution and protection information. Memory model: The TriCore architecture can access up to 4 Gbytes of unified program and I/O (Input/ Output) memory. The address width is 32-bits. The address space is divided into 16 regions or segments (0 through 15). Each segment is 256-Mbytes. The upper four bits of an address select the specific segment. The first 16-Kbytes of each segment can be accessed using either absolute addressing or absolute bit addressing with the bit se...

 Write 1 on Pin 16 in ODR Register  using 5 ways 1. Using numeric memory Address directly # define GPIO_ODR_ADDRESS 0X00010004 Void main() {  *(volatile uint32_t*)  GPIO_ODR_ADDRESS |= 1<16; } 2. Casting an address to a pointer # define GPIO_ODR ((volatile uint32_t*) GPIO_ODR_ADDRESS ) Void main() {  * GPIO_ODR |= 1<16; } 3. Casting to a pointer and then dereferencing it # define GPIO_ODR *((volatile uint32_t*) GPIO_ODR_ADDRESS ) Void main() {    GPIO_ODR |= 1<16; } 4. Use structure union and pointer for one register # define GPIO_ODR *((volatile uint32_t*) GPIO_ODR_ADDRESS ) #pragma pack(1) struct SGPIO_ODR_t {     uint32_t pin0:1;     uint32_t pin1:1;     uint32_t pin2:1;     uint32_t pin3:1;     uint32_t pin4:1;     ...     ...      ... } union U_ODR  {     struct SGPIO_ODR_t S_ODR;     uint32_t ODR; } volatile union U_ODR *GPIO_ODR...